Analog-to-digital converters (ADCs) are in widespread use. Essentially, the ADC converts a continuous analog signal into discrete bits by sampling the continuous analog signal and quantizing it into a set of discrete levels. There are various types of ADCs, each having different cost and performance characteristics. Algorithmic ADCs (also known as “cyclic” or “recirculating” ADCs) operate by amplifying a signal to be converted and comparing the amplified signal to a reference voltage. If the amplified signal is greater than the reference voltage, then the most significant bit (MSB) of the output code is set to one, and the reference is subtracted from the amplified signal. If the amplified signal is less than the reference voltage, the MSB is set to zero and there is no subtraction operation. The remaining part of the amplified signal is called the “residue voltage”. The residue voltage undergoes the same operation: it is amplified and compared to determine the next bit in the output code, and another residue voltage is developed. This process continues until the least significant bit (LSB) is obtained.
Because algorithmic ADCs perform a heavily serial operation using a simple circuit, they are area efficient and consume a low amount of power. The main disadvantage of algorithmic ADCs is their relatively long conversion cycle occasioned by its serial nature of operation. Typically, algorithmic ADCs use clock signals provided by a phase-locked loop (PLL) or crystal oscillator in which every clock pulse has an equal length. For applications such as video analog-to-digital conversion, having resolutions in the range of 7–14 bits and clock frequencies in the range of 20–50 MHz, this conversion cycle is too slow. Hence, algorithmic topologies have not been suitable for applications such as video ADCs having this speed and resolution range. Instead, other topologies such as pipeline topologies have been used.